Integrated circuits have progressed to advanced technologies with high packing densities and smaller feature sizes, such as 45 nm, 32 nm, 28 nm and 20 nm. In these advanced technologies, three dimensional transistors each having a multi-fin structure are often desired for enhanced device performance. However, existing methods and structures for such structures have various concerns and disadvantages associated with device quality and reliability. For example, various defects can be induced by merging an epitaxial (epi) feature. In another example, source and drain resistances are increased due to poor quality of merged source/drain epi features. In another example, the fabrication cost is higher due to additional process steps, such as the need for an additional mask to define an intra-device region. Therefore, there is a need for a new structure and method for a multi-fin device to address these concerns for enhanced performance and reduced fabrication cost.